|Yinan Xu 5986560e7d Update Artifact Evaluation badges to README.md (#1789)||1 day ago|
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XiangShan (香山) is an open-source high-performance RISC-V processor project.
Copyright 2020-2022 by Institute of Computing Technology, Chinese Academy of Sciences.
Copyright 2020-2022 by Peng Cheng Laboratory.
XiangShan-doc is our official documentation repository. It contains design spec., technical slides, tutorial and more.
Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors. It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc. This paper is awarded all three available badges for artifact evaluation (Available, Functional, and Reproduced).
Paper PDF | IEEE Xplore (TBD) | ACM DL (TBD) | BibTeX (TBD)
The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on the yanqihu branch, which has been developed since June 2020.
The second stable micro-architecture of XiangShan is called Nanhu (南湖) on the nanhu branch.
The current version of XiangShan, also known as Kunminghu (昆明湖), is still under development on the master branch.
The micro-architecture overview of Nanhu (南湖) is shown below.
Some of the key directories are shown below.
. ├── src │ └── main/scala # design files │ ├── device # virtual device for simulation │ ├── system # SoC wrapper │ ├── top # top module │ ├── utils # utilization code │ ├── xiangshan # main design code │ └── xstransforms # some useful firrtl transforms ├── scripts # scripts for agile development ├── fudian # floating unit submodule of XiangShan ├── huancun # L2/L3 cache submodule of XiangShan ├── difftest # difftest co-simulation framework └── ready-to-run # pre-built simulation images
make verilogto generate verilog code. The output file is
Makefilefor more information.
NEMU_HOMEto the absolute path of the NEMU project.
NOOP_HOMEto the absolute path of the XiangShan project.
AM_HOMEto the absolute path of the AM project.
mill. Refer to the Manual section in this guide.
make initto initialize submodules.
make emuto build the C++ simulator
./build/emu --helpfor run-time arguments of the simulator.
verilator.mkfor more information.
make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10 ./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so
In the development of XiangShan, some sub-modules from the open-source community are employed. All relevant usage is listed below.
|L2 Cache/LLC||Sifive block-inclusivecache||Our new L2/L3 design are inspired by Sifive's
|Diplomacy/TileLink||Rocket-chip||We reused the Diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus.|
We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the license.